NCP1651DR2G【PDF 22/32 页】IC PFC CONTROLLER CCM/DCM 16SOIC

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NCP1651

http://onsemi.com

Thereisahysteresisof30癈onthiscircuit,whichwillallow

the chip to cool down to 130癈 before resuming operation.

Whileintheovertemperatureshutdownmode,thestartup

circuit will be operational and the V

will cycle between

10.8 and 9.8 volts.

Insufficient V

If the level of the V

voltage is not

sufficienttomaintainoperation,thedriveofthechipwillbe

inhibited and the divide- -by- -eight timer will be invoked.

This will normally occur when the output is overloaded.

Underthiscondition,thedivide- -by- -eightcounterwillcount

for 8 V

cycles. At the end of the eighth cycle the driver

will be enabled and the circuit will attempt to start. If the

failure has been corrected, the output will come up and the

circuit will resume normal operation. If not, another cycle

will begin. The waveforms for overload timeout are shown

in Figure 3.

Shutdown

The NCP1651 has a shutdown circuit that

can be used to inhibit the operation of the chip by reducing

the FB/SD pin voltage to less than 0.6 volts. When a

shutdown signal is issued, the output of the shutdown

comparatorgoeslow.Thisimmediatelyceasestheoperation

of the unit by ORing that signal to the output of the PWM

logic, and holding the driver in its low state.

The inverted output of the shutdown comparator isfed in

to the reset pin of the divide- -by- -eight counter. The counter

reset pin sets its count to seven. As long as the reset pin is

low, the counter will remain at seven. When the shutdown

signalisremoved,theresetpinwillgohigh,andthecounter

will continue to count to eight. The counter is triggered on

the negative edge of the startup enable signal. This means

that a shutdown signal that is removed on the upward V

slopewillbeinthe7countfor theremainingriseandfallof

that V

cycle and will change to 8 on the next cycle.

Thissystemassuresthat the unit will not be enabled until

the V

voltage has a full discharge cycle available, and it

also insures that the unit will commence operation in less

than two V

cycles. A timing diagram of this mode of

operation is shown in Figure 3. The count for the

divide- -byeight counter is shown as 7, 7, 7, 8 which

illustrates the operation of the reset function.

If theshutdownsignalisterminatedbeforethe V

voltage

reaches the lower UVLO limit (i.e. 9.8 volts), the unit will

resumeoperationonthefollowingV

downslope,andifthe

shutdown signal is terminated on the V

upward slope, the

unit will resume operation on the second V

down slope.

AC Reference Buffer

The AC reference buffer converts the voltage generated

by the AC error amplifier to be converted into a current to

be summed with the ramp compensation signal and the

instantaneous current signal.

Figure 37. AC Reference Buffer Schematic

CURRENT

MIRROR

16 k

6.7 k

2.9 V

Unity Gain Amplifier

ERROR

AMP

Comp

PWM,

Ramp

Comp

Current

Sense

Amp

The buffers transfer function is:

out

= (2.9 V V

ac(ea)

)6.7 k

The buffer amplifier, converts the input voltage to a

current by creating a current equal to the voltage difference

between the AC error amplifier output and the 2.9 volt

reference dropped across the 6.7 k?resistor. The bipolar

transistor level shifts the voltage and maintains the proper

current into the current mirror. The current mirror has a

1:1 ratio and delivers its output current to the PWM input.

This current is summed with the currents of the ramp

compensationsignalandtheinstantaneouscurrentsignalto

determine the turn- -off point in the switching cycle.

Startup Circuit

Thestartupcircuitservesseveralfunctions.Inadditionto

providing the initial charge on the V

capacitor, it serves

asatimer for thestartup,overcurrent,andshutdownmodes

ofoperation.Duetothenatureofthiscircuit,thischipmust

be biased using the startup circuit and an auxiliary winding

on the power transformer. Attempting to operate this chip

off of a fixed voltage supply will cause the chipto latchup

in some modes of operation.

A high voltage FET is biased as a current source to provide

current for startup power. On the application of input voltage,

thehighvoltagestartupcircuitisenabledandcurrentisdrawn

from the rectified AC line to charge the V

cap.

WhenthevoltageontheV

capreachestheturnonpoint

for the UVLOcircuit (10.8voltstypical),the startupcircuit

is disabled, and the PWM circuit is enabled. With the

NCP1651 enabled, the bias current increases from its

standby level to the operational level. The divide- -by- -eight

counterispresettothecountof7,sothatonstartupthechip

will not be operational on the first cycle. The second V

cyclewillbenumber 8, andthe chipwill beallowed tostart

at thistime. In the shutdown mode, the V

cycle is held in

the 7 count state until the shutdown signal is removed. This

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